As radio frequency (RF) communication systems evolve, the range of frequency bands that transceivers within mobile communication devices are required to support continues to grow. Currently, a typical transceiver adapted to support communication within, for example, a Universal Mobile Telecommunications System (UMTS) may be required to support up to eleven distinct frequency bands.
Traditional frequency generation solutions utilise a Phase Locked Loop (PLL), which contains a Voltage Controlled Oscillator (VCO) that can be tuned over a range of frequencies. However, the cost of supporting a wide tuning range includes increased current consumption, a requirement for a higher quality of inductors that consume either significant amounts of silicon area or module board area, and increased design challenge to meet noise requirements simultaneously over all the supported frequency bands. Accordingly, in order to support the wide range of frequency bands required for UMTS transceivers and the like, conventional solutions require the use of two or more VCOs to provide two or more reference signals from which to generate required synthesized signals.
As will be appreciated, as process geometries shrink, the size of transistors within semiconductor devices is comparably becoming smaller. Conversely, the rate at which analogue components, such as capacitors and inductors, are becoming smaller is significantly less than the rate at which transistors are becoming smaller. The continual drive for reducing the size of integrated circuits and semiconductor devices has lead to a need to develop systems and devices that take advantage of the greater rate of reduction in the size of transistors, and thus digital components, whilst minimising the effect of the relatively slow rate at which analogue components are becoming smaller.
As will also be appreciated, VCOs comprise analogue components, which have become relatively bulky in terms of integrated circuits and semiconductor devices. Furthermore, VCOs require relatively large inductors, thereby further increasing the silicon area taken up by the presence of VCOs. Thus, VCOs are relatively expensive in terms of silicon area of a semiconductor device, and therefore have a direct effect on the cost of producing the semiconductor devices, since the greater the silicon area of a device, the fewer devices that can be manufactured from a single wafer.
FIG. 1 illustrates an example of a known Delay Locked Loop (DLL) Synthesizer 100, used to generate a plurality of synthesized frequency signals from a single VCO. The synthesizer 100 comprises a Phase-Locked Loop (PLL) 110, operably coupled to a local oscillator 120, for example a Voltage Controlled Oscillator (VCO). The PLL 110 is arranged to provide a control signal to the local oscillator 120, and as such to cause the local oscillator 120 to generate a fixed reference frequency signal fref 125. The synthesizer 100 further comprises M delay elements 130, operably coupled to delay control logic 140. The first delay element 132 receives the fixed reference frequency signal fref and introduces a delay to the reference signal fref 125. An identical delay is subsequently introduced by each of the M delay elements 130. The length of the delay introduced by each delay element 130 may be defined as T/M, where T is the period of the fixed frequency signal fref 125 generated by the local oscillator 120 and M is the number of delay elements. In this manner, the delay elements 130 output M component signals 150 with their corresponding edge transitions separated in time by T/M.
Thus, from a reference square wave signal in a form of the fixed reference frequency signal fref generated by the local oscillator 120, the delay elements 130 generate M square waves, in the form of component signals 150, comprising transition edges offset in time relative to one another by a period of T/M. These component signals 150 are then provided to digital processing logic 160, which selects which of the component signals 150 to output at any one time, in order to generate the required synthesized frequency signal 170. Only one component signal 150 is ever connected to the output at one time. In this manner, the output synthesized frequency signal 170 is constructed from the components signals 150.
FIG. 2 illustrates an example of a synthesized frequency signal 170 generated by the digital processing logic 160 of FIG. 1. As previously mentioned, the digital processing logic 160 receives the M component signals 150, and selects those component signals 150 to output at any one time, in order to generate the synthesized frequency signal fout 170. For the example illustrated in FIG. 2, M=6, and as such there are six component signals 210, 220, 230, 240, 250, 260 comprising edge transitions separated in time by T/6, where T is the period of a cycle 205 of the fixed frequency signal fref 125. The digital processing logic 160 is arranged to generate a synthesized frequency signal 170 comprising a period of 2T/3. Accordingly, the digital processing logic 160 selects component signals to output that will provide edge transitions corresponding to a synthesized signal comprising a period of 2T/3. Thus, for the example illustrated in FIG. 2, the digital processing logic 160 is initially configured to output the component signal 210 comprising the fixed frequency signal fref 125 delayed by T/6. In this manner, the synthesized frequency signal 170 comprises a falling edge transition 272 corresponding to a falling edge transition 212 of the selected component signal 210. The digital processing logic 160 then selects the component signal 260 comprising the fixed frequency signal fref 125 delayed by T. In this manner, the synthesized frequency signal 170 comprises a subsequent rising edge transition 274 corresponding to the rising edge transition 264 of the selected component signal 260. The digital processing logic 160 then selects the component signal 250 comprising the fixed frequency signal fref 125 delayed by 5T/6. In this manner, the synthesized frequency signal 170 comprises a subsequent falling edge transition 276 corresponding to the falling edge transition 256 of the selected component signal 250. As can be seen in FIG. 2, in this manner the digital processing logic 160 is able to select those component signals to output that provide edge transitions substantially T/3 apart, thus generating a synthesized frequency signal 170 comprising a period of 2T/3.
As will be appreciated, the use of such delay elements to progressively delay the fixed frequency signal fref in this manner results in the quantisation in time of the fixed frequency signal fref. Thus, in this manner, the synthesizer 100 is able to generate multiple synthesized frequency signals using only a single VCO 120.
However, a problem with known DLL synthesizers, such as synthesizer 100 of FIG. 1, is that the quantisation in time of the fixed frequency signal fref results in a creation of quantisation noise at synthesized frequencies requiring edge transitions that do not correspond precisely with those of the component signals. That is to say, if a required synthesized frequency signal comprises a period that is not a precise integer multiple of 2T/M, the edges of the required synthesized frequency signal will not coincide with edges of the component signals 150, and quantisation errors in time will occur. For example, if a desired synthesized frequency signal requires an edge that falls between the edges of adjacent component signals 150, for example as indicated at point 280 in FIG. 2, an instantaneous error due to quantisation of the time axis at this point will occur within the output synthesized frequency signal, resulting in frequency spurs within the output synthesized frequency signal.
According to “A DDS synthesizer with time domain interpolator”, Rahkonen, T; Eksyma, H; Proceedings of ICECS apox; 99, The 6th IEEE International Conference on Electronics, Circuits and Systems 1999 (Volume 1, Issue, 1999 Pages 327-330), peak spur energy in dBc is typically bounded according to the relationship: −20 log((M−1)*fref/fout). Furthermore, it is known that spur locations change with output frequency. For transceivers that do not use surface acoustic wave (SAW) technology, spurs need to be at or below the noise frequency to avoid reciprocal mixing. Accordingly, to achieve, say, a peak spur energy level of −168 dBc/Hz, 16,384 delay elements are required, which for a reference frequency signal fref of 1 GHz equates to each delay element comprising a delay increment of 61 fsec. As will be appreciated by a skilled artisan, this is an impractically small delay increment.
Accordingly, in order for a transceiver comprising such a synthesizer to be able to support up to eleven frequency bands within, for example, a Universal Mobile Telecommunications System (UMTS), without instantaneous errors occurring, it is still necessary for the synthesizer to utilise two or more VCOs.
Furthermore, in a full duplex system a transceiver is required to support simultaneous transmit and receive operations. FIG. 9 illustrates an example of a traditional transceiver architecture 900 where the transmitter and receiver frequency references 910, 920 are separately and independently generated. As will be appreciated, for such a traditional transceiver architecture 900, the VCOs and associated analogue components that are required to support, for example, the eleven frequency channels are each required to be duplicated, one for each of the transmit and receive frequency references 910, 920. Thus, the abovementioned problems are typically also duplicated in full duplex systems.
The Long Term Evolution (LTE) project for the third generation (3G) of mobile telecommunications currently being developed by the 3rd Generation Partnership Project (www.3gpp.com), which although not a committed standard, is expected to be for the most part implemented in the future, anticipates extending the number of frequency bands that are required to be supported within a UMTS network from eleven to fourteen. As a result, known frequency synthesizers require additional VCOs in order to support the extra frequency bands, thus further increasing the relative cost in terms of both silicon area and price of semiconductor devices therefor.